1. Field of the Invention
The present invention relates to semiconductor technology, and in particular, to a method for forming a nano size vertical nanowire structure.
2. Description of the Prior Art
Vertical transistors are being researched recently. In a vertical transistor, a vertical column, which may be a vertical nano-wire formed of a semiconductor material, is formed over a substrate, which may be a bulk semiconductor wafer or a semiconductor-on-insulator (SOI) wafer. A gate dielectric and a gate electrode are formed to encircle the nanowire, with the encircled portion of the nanowire forming the channel of the respective vertical transistor. A source and a drain are formed, with one underlying the channel, and the other overlying the channel. The vertical transistor has a gate-all-around structure since the gate may fully encircle the channel. With the all-around gate structure, the drive current of the vertical transistor is high and short-channel effects are minimized.